Authors: E. Alarcón, M. Iannazzo and J. Madrenas
Journal/Conference: Proceedings of the XII Conference Design of Integrated Circuits and Systems 1997 (DCIS97), Sevilla, November 1997, pp.241
.Abstract - In this paper, speed and noise issues are reviewed in switched-current memory cells, concerning the copying accuracy. Optimum criteria for added storing capacitors and design parameters are derived for both speed and noise, as a function of clock frequency. A merit factor is defined including both factors and is analytically shown to be dependent on the area of the copy transistor. AMS-0.8mm process HSPICE simulation results validate these analysis.