Abstract - A mixed-signal circuit that can emulate multi-layer perceptron neural networks is presented. The sequential processing provides a tradeoff between speed, power consumption and circuit area, allowing a flexible accommodation of different network structures. The design of the three most critical analog basic blocks of the processor is presented. a) Dynamic analog memories: A technique of switching error cancellation is proposed. b) Semialgorithmic DAC multipliers. They perform an analog-digital product., so the network parameters are stored in digital form. c) Sigmoid circuit. A winner-take-all based sigmoid circuit is used to fulfill the system requirements. The common-mode currents are cancelled by means of a common-mode feedback. Concerning the digital part, a general-purpose programmable digital control circuit with a high degree of circuit control flexibility is presented. Finally, the results and ongoing work are discussed.