Authors: Jordi Madrenas, Eduard Alarcón, J. Manuel Moreno and Jordi Cosp
Journal/Conference: Proceedings of the XIII Conference Design of Integrated Circuits and Systems 1998 (DCIS98), pp. 536-541, Madrid, 17-20 November 1998.
Abstract -The practical analog implementation of a neural architecture is presented. The modifications of this architecture enable an efficient implementation that among other benefits eliminates the signal degradation produced by shifting in the original systolic architecture. The most critical basic blocks design is presented, including a technique of switching error cancellation and the design of a semialgorithmic DAC multiplier. A compact and programmable digital control is presented as well. Finally, the results and future work are discussed.